1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a data driving circuit of a liquid crystal display that is adaptive for selectively switching and multiplexing voltages in accordance with a bit order of input data.
2. Discussion of the Related Art
A typical liquid crystal display controls light transmittance of liquid crystal cells in accordance with video signals to thereby display a picture. An active matrix type of liquid crystal display that includes a switching device for each liquid crystal cell is particularly suited for displaying moving pictures through active control of the switching devices. A thin film transistor (hereinafter, referred to as “TFT”) is typically used as the switching device in active matrix liquid crystal displays as shown in FIG. 1.
Referring to FIG. 1, a liquid crystal display of the active matrix type converts a digital input data into an analog data voltage on the basis of a gamma reference voltage and supplies the analog data voltage to a data line DL. Concurrently a scanning pulse is supplied to a gate line GL, to turn on the TFT to thereby charge a liquid crystal cell Clc from the analog voltage applied to the data line DL.
A gate electrode of the TFT is connected to the gate line GL, a source electrode is connected to the data line DL, and a drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc and to an electrode of a storage capacitor Cst.
A common electrode of the liquid crystal cell Clc is supplied with a common voltage Vcom.
When the TFT is turned-on, the storage capacitor Cst charges a data voltage applied from the data line DL and maintains the voltage charged to the liquid crystal cell Clc until a new data voltage is to be charged.
When a gate pulse is applied to the gate line GL, the TFT is turned-on to establish a conductive channel between the source electrode and the drain electrode to thereby supply a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc. The arrangement of liquid crystal molecules of the liquid crystal cell Clc are controlled by an electric field generated between the pixel electrode and the common electrode to modulate an incident light.
A configuration of a liquid crystal display of the related art including pixels having the above-described structure is shown in FIG. 2.
Referring to FIG. 2, the liquid crystal display 100 of the related art includes a liquid crystal display panel 110, a data driving circuit 120, a gate driving circuit 130, a gamma reference voltage generator 140, a backlight assembly 150, an inverter 160, a common voltage generator 170, a gate driving voltage generator 180, and a timing controller 190.
The liquid crystal display panel 110 includes a liquid crystal layer between two glass substrates. On the lower glass substrate of the liquid crystal display panel 110, the data lines DL1 to DLm and the gate lines GL1 to GLn cross each other with the data lines DL1 to DLm substantially perpendicular to the gate lines GL1 to GLn. The crossings of the data lines DL1 to DLm and the gate lines GL1 to GLn define liquid crystal cells. A TFT is provided at each crossing of a data line DL1 to DLm and a gate line GL1 to GLn. Each TFT supplies a data provided on a data line DL1 to DLm to the liquid crystal cell Clc in response to a scanning pulse applied to the gate electrode of the TFT. The gate electrode of each TFT is connected to one of the gate lines GL1 to GLn while the source electrode of the TFT is connected to one of the data line DL1 to DLm. Further, the drain electrode of each TFT is connected to the pixel electrode of the respective liquid crystal cell Clc and the corresponding storage capacitor Cst.
The TFT is turned-on in response to a scanning pulse applied via a gate line among the gate lines GL1 to GLn connect to the TFT gate. Upon turning-on of the TFT, a video data on the data line among the data lines DL1 to DLm that is connected to the drain of the TFT is supplied to the pixel electrode of a corresponding liquid crystal cell Clc.
The data driving circuit 120 supplies analog data voltages to the data lines DL1 to DLm in response to a data driving control signal DDC that is supplied from the timing controller 190. Further, the data driving circuit 120 samples and latches digital video data RGB that are supplied from the timing controller 190 and then converts latched data into analog data voltages for realizing a gray scale at the liquid crystal cell Clc of the liquid crystal display panel 110 on the basis of a gamma reference voltage supplied from the gamma reference voltage generator 140.
The gate driving circuit 130 sequentially generates a scanning pulse or a gate pulse in response to a gate driving control signal GDC and a gate shift clock GSC supplied from the timing controller 190 to be applied to each of the gate lines GL1 to GLn. The gate driving circuit 130 determines a high level voltage and a low level voltage of the scanning pulse in accordance with the gate high voltage VGH and the gate low voltage VGL supplied from the gate driving voltage generator 180.
The gamma reference voltage generator 140 receives a high-level power voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage and supplies the positive and negative gamma reference voltages to the data driving circuit 120.
The backlight assembly 150 is provided at the rear side of the liquid crystal display panel 110, and is energized by an AC voltage and current supplied from the inverter 160 to irradiate a light onto each pixel of the liquid crystal display panel 110.
The inverter 160 converts a square wave signal generated at the interior thereof into a triangular wave signal, and then compares the triangular wave signal with a direct current power voltage VCC supplied from the system to generate a burst dimming signal proportional to the result of the comparison. When the burst dimming signal is generated, a driving integrated circuit IC (not shown) controls a generation of the AC voltage and a current within the inverter 160 to controls the generation of AC voltage and current to be supplied to the backlight assembly 150 in accordance with the burst dimming signal.
The common voltage generator 170 receives a high-level power voltage VDD to generate a common voltage Vcom, and supplies the common voltage Vcom to the common electrode of the liquid crystal cell Clc provided at each pixel of the liquid crystal display panel 110.
The gate driving voltage generator 180 is supplied with a high-level power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL, and supplies the generated gate voltages to the gate driving circuit 130. Herein, the gate driving voltage generator 180 generates a gate high voltage VGH having a voltage level greater than a threshold voltage of the TFTs provided at each pixel of the liquid crystal display panel 110 and a gate low voltage VGL a voltage level less then the threshold voltage of the TFTs. The gate high voltage VGH and the gate low voltage VGL generated in this manner are used to establish a high level voltage and a low level voltage respectively of the scanning pulse generated by the gate driving circuit 130.
The timing controller 190 supplies digital video data RGB provided from an external system such as a TV set or a computer monitor, to the data driving circuit 120. In addition, the timing controller 190 generates a data driving control signal DCC and a gate driving control signal GDC using horizontal/vertical synchronization signals H and V in response to a clock signal CLK and supplies the data driving control signal DCC and the gate driving control signal GDC to the data driving circuit 120 and the gate driving circuit 130, respectively. As shown, the data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, and a source output enable signal SOE. The gate driving control signal GDC includes a gate start pulse GSP and a gate output enable signal GOE.
The structure and function of a data driving circuit of the related art included in the above described liquid crystal display will be described in detail hereinafter.
Referring to FIG. 3, a data driving circuit 120 of the related art includes a decoder 121, a switching part 122, a multiplexing part 123, and an output buffer 124. The decoder 121 receives 3 bits of data and outputs eight selection signals to the switching part 122. The switching part 122 switches a gamma reference voltage from the gamma reference voltage generator 140 in accordance with eight selection signals from the decoder 121 to output a first voltage V1 and a second voltage V2. The multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 in accordance with a supplied plurality of 3 bit data. In other words, the multiplexer outputs 8 voltages each having output levels of either the first voltage V1 or the second voltage V2, with the pattern of voltage levels among the 8 outputs determined by the supplied 3 bit data. The output buffer 124 is driven by the first voltage V1 and the second voltage V2 that are multiplexed by the multiplexing part 123 to buffer an input data.
The multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 in accordance with a received plurality of 3 bit data to output voltages having the first and second voltage levels, V1 and V2 to selective ones of the first to eighth output terminals Vo1 to Vo8. The multiplexing and outputting functions of the multiplexing part 123 will be described in detail with reference to FIG. 4.
Referring to FIG. 4, if ‘000’ data are received, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output eight first voltages V1, using the first to eighth output terminals Vo1 to Vo8, to the output buffer 124.
If ‘001’ data are input, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output seven first voltages V1, via the first to seventh output terminals Vo1 to Vo7, to the output buffer 124, respectively and, at the same time output one second voltage V2, via the eighth output terminal Vo8, to the output buffer 124.
If ‘010’ data are input, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output six first voltages V1, via the first to sixth output terminals Vo1 to Vo6, to the output buffer 124 respectively and, at the same time output two second voltage V2, via the seven and eighth output terminals Vo7 and Vo8, to the output buffer 124, respectively.
If ‘011’ data are input, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output five first voltages V1, via the first to fifth output terminals Vo1 to Vo5, to the output buffer 124, respectively and, at the same time output three second voltages V2, via the sixth to eighth output terminals Vo6 to Vo8, to the output buffer 124, respectively.
If ‘100’ data are input, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output four first voltages V1, via the first to fourth output terminals Vo1 to Vo4, to the output buffer 124, respectively and, at the same time output four second voltages V2, via the fifth to eighth output terminals Vo5 to Vo8, to the output buffer 124, respectively.
If ‘101’ data are input, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output three first voltages V1, via the first to third output terminals Vo1 to Vo3, to the output buffer 124, respectively and, at the same time output five second voltages V2, via the fourth to eighth output terminals Vo4 to Vo8, to the output buffer 124.
If ‘110’ data are input, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output two first voltages V1, via the first and second output terminals Vo1 and Vo2, to the output buffer 124, respectively and, at the same time output six second voltages V2, via the third to eighth output terminals Vo3 to Vo8, to the output buffer 124, respectively.
If ‘111’ data are input, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output one first voltage V1, via the first output terminal Vo1, to the output buffer 124 and, at the same time output seven second voltages V2, via the second to eighth output terminals Vo2 and Vo8, to the output buffer 124, respectively.
The output buffer 124 includes a current source 124-1, eight NMOS transistors N_TR1 to N_TR8, and eight NMOS transistors N_TR9 to N_TR16. The current source 124-1 switches the applied current to a ground. The first eight NMOS transistors N_TR1 to N_TR8 are driven by the first voltage V1 or the second voltage V2 output from the multiplexing part 123 to supply a current from a load 124-2 to the current source 124-1. The second eight NMOS transistors N_TR9 to N_TR16 are driven by a voltage from the load 124-2 to supply a current from the load 124-2 to the current source 124-1. The eight NMOS transistors N_TR1 to N_TR8 and the eight NMOS transistors N_TR9 to N_TR16 are arranged to be symmetrical to each other.
The NMOS transistor N_TR1 includes a gate that is connected to the first output terminal Vo1 of the multiplexing part 123, a drain that is connected to the load 124-2, and a source that is connected to the current source 124-1. The NMOS transistor N_TR1 is driven by the first voltage V1 that is output via the first output terminal Vo1 of the multiplexing part 123 to supply a current from the load 124-2 to the current source 124-1.
The NMOS transistor N_TR2 includes a gate that is connected to the second output terminal Vo2 of the multiplexing part 123, a drain that is connected to the load 124-2, and a source that is connected to the current source 124-1. The NMOS transistor N_TR2 is driven by the first voltage V1 or the second voltage V2 that is output via the second output terminal Vo2 of the multiplexing part 123 to supply a current from the load 124-2 to the current source 124-1.
The NMOS transistor N_TR3 includes a gate that is connected to the third output terminal Vo3 of the multiplexing part 123, a drain that is connected to the load 124-2, and a source that is connected to the current source 124-1. The NMOS transistor N_TR3 is driven by the first voltage V1 or the second voltage V2 that is output via the third output terminal Vo3 of the multiplexing part 123 to supply a current from the load 124-2 to the current source 124-1.
The NMOS transistor N_TR4 includes a gate that is connected to the fourth output terminal Vo4 of the multiplexing part 123, a drain that is connected to the load 124-2, and a source that is connected to the current source 124-1. The NMOS transistor N_TR4 is driven by the first voltage V1 or the second voltage V2 that is output via the fourth output terminal Vo4 of the multiplexing part 123 to supply a current from the load 124-2 to the current source 124-1.
The NMOS transistor N_TR5 includes a gate that is connected to the fifth output terminal Vo5 of the multiplexing part 123, a drain that is connected to the load 124-2, and a source that is connected to the current source 124-1. The NMOS transistor N_TR5 is driven by the first voltage V1 or the second voltage V2 that is output via the fifth output terminal Vo5 of the multiplexing part 123 to supply a current from the load 124-2 to the current source 124-1.
The NMOS transistor N_TR6 includes a gate that is connected to the sixth output terminal Vo6 of the multiplexing part 123, a drain that is connected to the load 124-2, and a source that is connected to the current source 124-1. The NMOS transistor N_TR6 is driven by the first voltage V1 or the second voltage V2 that is output via the sixth output terminal Vo6 of the multiplexing part 123 to supply a current from the load 124-2 to the current source 124-1.
The NMOS transistor N_TR7 includes a gate that is connected to the seventh output terminal Vo7 of the multiplexing part 123, a drain that is connected to the load 124-2, and a source that is connected to the current source 124-1. The NMOS transistor N_TR7 is driven by the first voltage V1 or the second voltage V2 that is output via the seventh output terminal Vo7 of the multiplexing part 123 to supply a current from the load 124-2 to the current source 124-1.
The NMOS transistor N_TR8 includes a gate that is connected to the eighth output terminal Vo8 of the multiplexing part 123, a drain that is connected to the load 124-2, and a source that is connected to the current source 124-1. The NMOS transistor N_TR8 is driven by the first voltage V1 or the second voltage V2 that is output via the eighth output terminal Vo8 of the multiplexing part 123 to supply a current from the load 124-2 to the current source 124-1.
The eight NMOS transistors N_TR9 to N_TR16 each have a gate and a drain that are connected to the load 124-2, and a source that is connected to the current source 124-1. The eight NMOS transistors N_TR9 to N_TR16 are each driven by a voltage from the load 124-2 to supply a current from the load 124-2 to the current source 124-1.
As described above, in the data driving circuit of the related art, the multiplexing part 123 receives n bits data to output 2n voltages to the output buffer 124. Thus, the number of output terminals of the multiplexing part 123 and the number of signal lines connected to the output terminal are doubled for each unit increase in the number of bits of input data. As a result, there is a problem in that the data driving circuit has a complex structure and occupies a large area.